With the development of a liquid crystal display apparatus with high definition and high performance, a liquid crystal, driver (IC chip) incorporated in the liquid crystal display apparatus is required to have an increased number of outputs, and also a reduced chip size.
In order to accomplish the increased number of outputs in an IC chip reduced in chip size, it is required for the chip to have bumps made in a fine pitch (smaller pitch). Recently, an SOF (System On Film), also referred to as COF (Chip On Film)) is often used. The SOF can realize the fine pitch and includes a bare chip liquid crystal driver.
In the latest SOF package, inner leads on a tape carrier are bonded to bumps on an IC chip by the application of heat and pressure so that the tape carrier is brought into conduction with the IC chip. However, such a bonding method requires a very fine tape carrier material which is less susceptible to heat deformation to prevent misalignment between bumps and inner leads. In other words, the realization of a fine pitch limits a choice of material for a tape carrier.
Moreover, the inner leads are made of copper foil; in order to carry out wire processing in fine pitch, it is required to reduce thickness of the copper foil. For example, a copper foil for a TCP having a pitch of 50 μm has a thickness of 12 μm; in order to form a pitch of 20 μm, the thickness of the copper foil requires to be around 5 μm. In order to maintain strength while providing a thin copper foil, it is required to introduce new techniques and new processing apparatuses by reviewing the currently used techniques. This causes costs required in labor work for discussing techniques and costs for introducing new equipment.
Furthermore, in a case where the wires are processed, if a processing accuracy of the processing apparatus sufficiently surpasses a wire pitch, a test that follows the processing may be carried out to just a simple degree. However, if the wires are finely pitched, and the processing accuracy is closer to the wire pitch, a thorough test is necessarily carried out after the processing, of whether or not there is a part left that is insufficiently processed, or the like. This causes an increase in testing costs.
As a method of solving such a problem, Patent Literature 1 (Japanese Patent Application Publication, Tokukai, No. 2004-207566 A (published on Jul. 22, 2004) discloses a method in which an IC chip is connected to a circuit board (tape carrier) via an interposer substrate. FIG. 12 illustrates a cross sectional view of a package structure described in Patent Literature 1.
As illustrated in FIG. 12, an IC chip 104 is connected to an interposer 101 by flip chip bonding. The interposer 101 is further connected to a terminal pattern 110 of a circuit board 107 by bump bonding. The circuit board 107 has a device hole 107A which corresponds to a region in which the IC chip 104 is provided.
The interposer 101 is a silicon (Si) substrate and is formed in a Si wafer process. This makes it possible to form electrodes of the interposer 101 which electrodes are connected to the electrodes of the IC chip 104, at a pitch as fine as that of the electrodes of the IC chip 104. On the other hand, electrodes of the interposer 101 which electrodes are connected to the circuit board 107 are formed at a pitch that agrees with a pitch of the electrodes of the circuit board 107, which pitch is relatively large. The electrodes connected to the IC chip 104 are connected to the corresponding electrodes connected to the circuit board 107, on the interposer 101. As the circuit board 107, a tape carrier can be used.
A part where the circuit board 107, the IC chip 104, and the interposer 101 are connected are sealed with sealing resin, so as to be protected from external environment.
In other words, the interposition of the interposer 101 as illustrated in FIG. 12 allows a fine pitch of the IC process to be changed to an electrode pitch of the tape carrier. Hence, it is possible to avoid increase in manufacturing cost and testing costs even with the use of an SOF package in which an IC chip whose connecting terminals are provided at a very fine pitch is included for reduced size or increased outputs of the IC chip.